I absolutely love PlantUML, so thank you for all of your work.
I work with embedded microcontrollers and I have a need to create timing diagrams on a daily basis (which is one thing that brought me to PlantUML). However, there are a few requests that I have to make the timing a little more efficient for my needs.
Most of the time, I am working with binary signals, clocks, and data buses.
- specifiy "clock" with a time period, diagram will auto fill the length of the waveform
- allow multiple lines in one frame, for more compact diagram
- allow signal change to track on events instead of on absolute time
- allow for a "break" in time. and ellipse if you will, to show some time has passed.
- allow a timing diagram without specific times. A lot of my diagrams are more event based (enable line went high, +3 clock cycles the data line is accepted).
- Being able to specify the entire wave cycle of a signal on one line of code would be nice (see wavedrom), but not entirely necessary.
These are just the few things that I can think of off of the top of my head.
At the moment, I use plantUML for all of my state diagrams; but when I need timing, I keep defaulting back to "WaveDrom" https://wavedrom.com/tutorial.html . Which produces very nice results, but also has its limitations. you can see how concise the full diagrams are, which is desirable. You can specify events, but only 26 of them, as you can only use "characters" to define them, which i find limiting. The events allows arrows to point, which is perfect, but the events are not tracked to a certain 'event'; they are simply defined in congruent spatial reference with the wave event. Ideally, I would prefer to be able to set an event, much like in your gantt charts, and then have stuff referenced off of that.
an example might be as follows: this describes a clock, databus, and data ready signal. The databus and signal will reference the clock line for their timing. At some amount of clock cycles, the databus will fill with a value. Once filled it will be 'X' many clock cycles until the ready signal is sent.
clock "clk" as myClk
myClk period is 200ns
Binary Bus "Data Bus" as db
Binary Signal "Data Ready" as dr
0 is UNDEFINED
+4 myClk is 0x354 as dataStart
0 is low
+5 myClk from dataStart is high
Please let me know if something like this is doable, I would love to help in any way I can to see this stuff worked out. If there are already things in place for this, please let me know, and I would be happy to create examples for the website.