Hello!
I'm making a Component Diagram and i'm having lots of questions about internal logic of PlantUML.
See linked picture (https://photos.app.goo.gl/3daiUUTMoStdXCvw7). I've marked numbers on it:
1) Here elements overlap each other, ignoring that there's enough space in the parent component
2) Here size of the component is totally bigger than required. Why so much empty space on the left and right? Also why internal components are not centered of anything?
3 and 4) Why portout is placed in that weird place? Usually portin is placed on the left side, portout is placed on the right side of the component. But in this particular component (two instances, which are basically copy-paste+rename) portout is placed this way?
(I've experimented here and found that this happens as soon as I add a connection from portin to element "Буфер", and from element "Буфер" to element "Обработка". Without these connections portout is placed on the right side, as i should be)
5) Why these components are placed this way? I have ordered the system to use left to right placement.
Basically these are the questions. It would be great to know if it is possible to fix/adjust this.
Thanks
And the program:
@startuml
!include <edgy/edgy>
skinparam componentStyle rectangle
skinparam component {
BackgroundColor lightblue
BorderColor black
FontSize 20
Padding 5
}
left to right direction
package "Instance 1" {
component [Входы] as VIN {
portout " " as vin_p
[Карта SDI] as vin1
[Карта ...] as vin2
[...] as vin3
vin1 --> vin_p
vin2 --> vin_p
vin3 --> vin_p
}
component [Приемник] as receiver {
portin " " as r_in
portout " " as r_out
}
component [Буфер\nисходных_кадров] as src_buff {
portin " " as src_buf_in
portout " " as src_buf_out
[Видео] as src_buf_v
[Аудио] as src_buf_a
}
note bottom of src_buff
Размер - один кадр
end note
component [Обработчик] as processor {
portin " " as p_in
portout " " as p_out
portout " " as p_out2
[Буфер] as p_b
[Обработка] as p_p
p_in ..> p_b
p_b ..> p_p
p_p .> p_out
p_p -[dashed]-> p_out2
}
component [Буфер\nготовых_кадров] as out_buff {
portin " " as out_buf_in
portout " " as out_buf_out
[Видео] as out_buf_v
[Аудио] as out_buf_a
}
note bottom of out_buff
Размер - один кадр
end note
component [Мультиплексор] as sender {
portin " " as s_in_main
portin " " as s_in_second
portout " " as s_out
}
component [Выходы] as VOUT {
portin " " as vout_in
[Карта SDI] as vout_1
[Карта ...] as vout_2
[...] as vout_3
vout_in ..> vout_1
vout_in ..> vout_2
vout_in ..> vout_3
}
vin_p --> r_in
r_out --> src_buf_in
src_buf_out --> p_in
src_buf_out -[#FF0000,dashed]-> s_in_second
p_out --> out_buf_in
out_buf_out -[#00FF00,dashed]-> s_in_main
s_out --> vout_in
}
' package Instance 1
left to right direction
package "Instance 2" {
component [Обработчик] as processor2 {
portin " " as p2_in
portout " " as p2_out
[Буфер] as p2_b
[Обработка] as p2_p
p2_in ..> p2_b
p2_b ..> p2_p
p2_p ..> p2_out
}
component [Буфер\nготовых_кадров] as out_buff2 {
portin " " as out_buf2_in
portout " " as out_buf2_out
[Видео] as ob2_v
[Аудио] as ob2_a
}
note bottom of out_buff2
Размер - один кадр
end note
component [Мультиплексор] as sender2 {
portin " " as m2_in_main
portin " " as m2_in_second
portout " " as m2_out
}
component [Выходы] as vout2 {
portin " " as vout2_in
[Карта SDI] as vout2_1
[Карта ...] as vout2_2
[...] as vout2_3
vout2_in ..> vout2_1
vout2_in ..> vout2_2
vout2_in ..> vout2_3
}
p2_out -right-> out_buf2_in
out_buf2_out -[#00FF00,dashed]-> m2_in_main
m2_out --> vout2_in
}
' package Instance 2
'. Время
package "Время" {
component [Источник_опорного_времени] as time_receiver {
portout " " as timer_out
}
component [Процессор_времени] as time_processor {
portin " " as timep_in
portout " " as timep_out
}
}
' package Время
src_buf_out --> p2_in
src_buf_out -[#FF0000,dashed]-> m2_in_second
timer_out .[#0000FF,dashed].> timep_in : [внешнее_время]
timep_out .[#0000FF,dashed].> receiver : [внутреннее время]
timep_out .[#0000FF,dashed].> processor
timep_out .[#0000FF,dashed].> processor2
timep_out .[#0000FF,dashed].> sender
timep_out .[#0000FF,dashed].> sender2
@enduml
