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2 answers
[Timing diagram] Improve clock pulse management
asked Oct 5, 2021 in Wanted features by The-Lu (92,280 points)
0 votes
1 answer
Include from embedded iuml cases Syntax Error
asked Nov 26, 2021 in Bug by boshka (4,060 points)
0 votes
1 answer
Swimlane repeat loop
asked Nov 15, 2021 in Bug by rod_makin (180 points)
0 votes
1 answer
[UseCase] Problem to apply syle class on use case
asked May 6, 2021 in Bug by Bada (120 points)
+1 vote
1 answer
Restricting the width of diagrams
asked Nov 24, 2017 in Wanted features by MSel
0 votes
1 answer
"Ghost links" between diagrams
asked Apr 16, 2020 in Bug by Soeren
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