Is there any way to produce "block diagrams"?

+3 votes
asked Mar 27, 2020 in Wanted features by mcon (120 points)

Is there any provision to produce block diagrams like these?


or, even better:

CL-SOM-iMX7 NXP i.MX7 System-on-Module block diagram

In case this is not possible, would it be considered for future enhancements?

I could help as I have a fair background in parsers and data generation, but I know virtually nothing about PlantUML innards and my java abilities may be "a bit rusty" as I'm using other languages since several years now.

commented Mar 30, 2020 by awschult (260 points)

This is a feature that I would really like to see. I asked about something very similar before (it was supposed to be a stepping stone towards this), but i didn't really get a great answer. I really hope they give a better response to yours.

What you have as examples are most ideal, and i would like to tell the developers to focus on the second one. That is what some consider to be an "I" chart. with some language, you can simply specify a list of boxes for the middle, then a list of boxes to each side, then connections between them, then group boxes. The layout would just be generated top down with in-line connections where possible. I would think a beta cut would be pretty decent.

i would also love to give the development a try, but i have never Java'd before and i don't have a ton of time at the moment to learn.

1 Answer

0 votes
answered Apr 6, 2020 by plantuml (250,820 points)

There are many requests for block diagrams.

The good news is that we have started to do some experiments...

This is really a preliminary version so don't expect anything real useful right now. However, you can play with the syntax and tell us what you think about it.

Some example:

I suggest that you try to generate the Freescale example. Right now, you cannot do link or lines.

We will improve the syntax according to the need of this example.

What do you think about it ?

commented Apr 6, 2020 by Serge Wenger Work (13,940 points)


Very nice. Some suggestions:

  • Add the possibility to give hspace (horizontal space)
  • Cannot put block in block with defined size:

component A [500x300] {
  component A0
  component Panel1
  component Panel2 [150x200]

  • The vspace inside block do nothing . In your example

component FGPA
  right:SDIA, CKIA, +5VDC
  right vspace 50
  right:SDIA_, CKIA_, +5VDC_
  component USB [20X50]

  • Add  "left, middle and right (or asolute offset ) for lateral positionning of blocks
  • Name blocks and IO to be able to connect easily after. Connections are often 1 to 1, but sometimes 1->n or n->1
Thanks for this new exciting feature

commented Aug 13, 2020 by awschult (260 points)
edited Aug 13, 2020 by awschult

I am a little concerned that we are starting off a little too wordy. I do like that we can add connector points to the blocks, but I think that arrows to and from blocks would be a little more important.

I think it would be nice to be able to say "X is left of Y" or " Y is above Z". Or you could use the same syntax as seen in other diagrams such as "X -right-> Y" or "X -down-> Z". That way syntax translates more easily.

I think restricting the layout engine to only pick 1 center object, then the rest get placed left/right/above/below and spaced evenly would give good results to start. More complex diagrams could be created by recursing that same layout to within other objects.

It took me a little while to figure out what your "right:" and "left:" statements where doing. I think changing the syntax there to "connector "RTN" is left" and "connector "VCC" is top" would make it more clear.

I am just concerned that we are going to end up with a syntax is becomes really cumbersome to create a small 4 block diagram.

If I were to try to create the freescale diagram above, I think I would like to see something akin to the following.

component FreeScale_SOC {

    component "Arm Cortex M4" as M4

    component "DDR3 Memory Controller" as DDRc

    component "Multifunctional signals" {

        component UART

        component CAN




        } as MUX

} as MX7

component DDR3

component SODIMM

SODIMM is right of MX7

MUX <-> SODIMM: "up to 7x UART"

MUX <-> SODIMM: "up to 2x CAN"

DDR3 is left of MX7

DDR3 <=> DDRc : "32 bit"

component PMIC is left of MX7