is there a simple way to use PlantUML to draw hardware block diagram?

0 votes
asked Nov 26, 2020 in Wanted features by Nir

More specificaly

block should have:

1. input port

2. output port

3. bus widths

4. connection to other port

1 Answer

0 votes
answered Nov 27, 2020 by The-Lu (19,860 points)

Hello N.,

What kind of hardware block diagram would you like design by PlantUML?

For starting point, you can see on 'State diagram' or on 'Wire diagram' (feature under development):

1/ State diagram


[See on PlantUML server]

See documentation on:

2/ Wire diagram

@startwire
vspace 100
component Panel10
  right:DSRE,SFVC,12VDV,12TRN
  bottom:TRIGIN,TRIGOUT

vspace 50
component Panel2 [50x150]
--
component FPGA [100x400]
  left:DSRE,SFVC,12VDV,12TRN
  right:SDIA, CKIA, +5VDC
  right vspace 10
  right:SDIA_, CKIA_, +5VDC_

vspace 50
component Reactor [100x200]
--
component MCD_A
vspace 30

component MCD_B
vspace 30

component MCD_C
vspace 30

component MCD_D
@endwire


[See on PlantUML server]


See also documentation:

If that can help,
Regards,
Th.

commented Nov 28, 2020 by Nir elkayam

Thank you for the reply

The wire diagram look the correct framework but I don't see where and how to add wires and also describe the ports, ie, name the ports

commented Nov 30, 2020 by plantuml (250,820 points)
This is really pre-alpha version, so you really cannot use it right now.

Furthurmore, this development is frozzen because we have too many work to do !

Really sorry about that.
commented Dec 15, 2020 by awschult (260 points)
The pre-alpha wireframe that you have posted is something that I have been asking about for a while (which you have told me this is coming.). But I see that it's frozen now. This is a feature that I, and many in my company would like to have available. Would some amount of donation help to unfreeze the development on it?
commented Dec 15, 2020 by plantuml (250,820 points)
Thanks for your donation proposal but it's really a question of time. So no need for donation, really sorry about that.

If you really want to see this going on, I suggest that you (and your collegues) begin to write on http://alphadoc.plantuml.com/doc/markdown/en/wire-diagram some examples of syntax your are expecting, with some links to some existing ressources. This wiki is simple to use and open (no need to create account).

Please start with simple examples. It would help us to better understand your needs and to see what we could do.
commented Dec 16, 2020 by awschult (260 points)
We will gladly help out!
commented Dec 19, 2020 by plantuml (250,820 points)

Thanks for your contributions, it really helps us in our design and thinking.

So last release 1.2020.24 proposes a brand new syntax for wire diagram.

We have updated the examples on http://alphadoc.plantuml.com/doc/markdown/en/wire-diagram

Even if it's a first release, it seems to us as a real improvement over previous proposals.

Now the experience on other diagrams show us that only trying and playing from users can tell if an idea is a good one or not. So your time to work now :-)

Please test this new syntax on some examples of yours, and tell us the pro & cons of this new approach. The best way to go is to put suggestions on the wiki itself.

commented Dec 24, 2020 by plantuml (250,820 points)

We've just publish a beta http://beta.plantuml.net/plantuml.jar with new feature

http://alphadoc.plantuml.com/doc/dokuwiki/en/wire-diagram has been updated

Happy testing :-)

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