How can I hide parts of a robust state in timing-diagram?

Question

In timing-diagram I can only hide a part of a concise state with "... is {hidden}" but not a robust state. If I do {hidden} appears as an extra line.

Answer 1

Not sure to get the idea :-)

Could you post a few examples so that we better understand your need ? Thanks!

Comments

My code:

https://drive.google.com/file/d/1SGEXLvjknCArHFBQjnd_8ShIx9NTR5Uq/view?usp=sharing

The generated picture:

https://drive.google.com/file/d/1A_AsN6VE5bbX0BoFVyg-Ram5Woiq7USU/view?usp=sharing

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Is anything wrong because you do not response?

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Everything is fine ! Thanks for your example, it really helps!

We had better understood your request.

This has been fixed in last beta http://beta.plantuml.net/plantuml.jar and on the online server.

@startuml
scale 1 as 50 pixels

concise state0
concise substate1
robust bit2

bit2 has HIGH,LOW

@state0
0 is 18_start
6 is s_dPause
8 is 10_data
14 is {hidden}

@substate1
0 is sSeq
4 is sPause
6 is {hidden}
8 is dSeq
12 is dPause
14 is {hidden}

@bit2
0 is HIGH
2 is LOW
4 is {hidden}
8 is HIGH
10 is LOW
12 is {hidden}
@enduml

Tell us if it's not what you were expecting !

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Thanks very much for the fix. This was exactly what I was asking for.

Am I aloud to add a little wish?

Could it be possible that you draw a vertical line from "LOW" to "HIGH" if I start with "0 is HIGH" and "8 is HIGH" even though the before state of the signal is not known or intricated?