How do I mark a binary as indeterminate in a timing diagram?

Question

In the embedded software and Verilog/VHDL world, a binary signal wire is frequently marked as "X" (at an indeterminate state, sometimes also called a "don't care" state) during initialization.  It looks like that is reflected in intricated states for "robust" signals.  A binary signal at at indeterminate state would be represented graphically the same way that an intricated signal is.  Is there any chance that could be added as a feature (if it isn't already)? 

Comments

See also pseudo-similar request here:

• https://forum.plantuml.net/11936/for-timing-diagram-binary-data-allow-data-to-be-indetermine

Regards.

Answer 1

The online server now allows this:

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