How do I mark a binary as indeterminate in a timing diagram?

+1 vote
asked May 6 in Wanted features by kepler2 (140 points)

In the embedded software and Verilog/VHDL world, a binary signal wire is frequently marked as "X" (at an indeterminate state, sometimes also called a "don't care" state) during initialization.  It looks like that is reflected in intricated states for "robust" signals.  A binary signal at at indeterminate state would be represented graphically the same way that an intricated signal is.  Is there any chance that could be added as a feature (if it isn't already)? 

commented May 8 by The-Lu (44,040 points)

1 Answer

+1 vote
answered 5 days ago by plantuml (273,920 points)
selected 5 days ago by kepler2
Best answer

The online server now allows this:

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