Ability to Draw Transfer Function Block Diagrams for Signal Processing?

0 votes
asked May 29, 2021 in Wanted features by DomasAquinas

I'm a new PlantUML user and already a big fan. I found the tool while looking for something handy to use for drawing class diagrams for a software architecture course, but then I saw that it could also create timing diagrams, and I've since been recommending it to coworkers.

I work as a signal processing engineer and FPGA circuit designer, so having a way to code up a timing diagram for a digital design in a hurry is awesome. I'm wondering whether there is - or could be - support for drawing system block diagrams for signal processing algorithms (e.g. adders, multipliers, delays, etc.). Since my company is increasingly moving toward using tools like Confluence, which include PlantUML support, being able to generate as much of our design documentation as possible in PlantUML is a plus, as we can display it on project pages and keep the text files in version control.

If something like this already exists, please pardon my inexperience and point me to the right documentation. :^)

If not, I appreciate any consideration.


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