[Timing diagram] Clock start

Question

I'm looking for a way to create a clock signal with an initial off state.  For example, a signal which is low for say 100us until a CLK_ENABLE signal is asserted high, after which the signal behaves like a clock signal with a 10us period.

Answer 1

Hello A.,

For that you can use offset, as:

@startuml
scale 50 as 100 pixels

binary "CLK_ENABLE" as en
clock "clka" as C0 with period 10 offset 100

@0
en is low

@100
en is high

@150
@enduml

See also:

• https://forum.plantuml.net/14647/timing-diagrams-can-we-get-an-offset-for-clocks

Enjoy,
Regards,
Th.