clock signal

Question

many times timing diagram involves clock signal. It would be nice to have clock signal auto-generated just by mentioning its inclusion within diagram. Otherwise, it would be annoying to specify when it should be 0 and when it should be 1. Controlling clock cycle time is also desired.

Answer 1

Hello

I think it's solved since the beta version 2020

https://forum.plantuml.net/9053/timing-diagrams-for-binary-signal-and-data-buses?show=9053#q9053