Timing Diagrams for Binary Signal and Data buses

+1 vote
asked Feb 25, 2019 in Wanted features by awschult (360 points)
edited Feb 25, 2019 by awschult

I absolutely love PlantUML, so thank you for all of your work.

I work with embedded microcontrollers and I have a need to create timing diagrams on a daily basis (which is one thing that brought me to PlantUML). However, there are a few requests that I have to make the timing a little more efficient for my needs.

Most of the time, I am working with binary signals, clocks, and data buses. 

  • specifiy "clock" with a time period, diagram will auto fill the length of the waveform
  • allow multiple lines in one frame, for more compact diagram
  • allow signal change to track on events instead of on absolute time
  • allow for a "break" in time. and ellipse if you will, to show some time has passed.
  • allow a timing diagram without specific times. A lot of my diagrams are more event based (enable line went high, +3 clock cycles the data line is accepted).
  • Being able to specify the entire wave cycle of a signal on one line of code would be nice (see wavedrom), but not entirely necessary.

These are just the few things that I can think of off of the top of my head.

At the moment, I use plantUML for all of my state diagrams; but when I need timing, I keep defaulting back to "WaveDrom" https://wavedrom.com/tutorial.html  . Which produces very nice results, but also has its limitations. you can see how concise the full diagrams are, which is desirable. You can specify events, but only 26 of them, as you can only use "characters" to define them, which i find limiting. The events allows arrows to point, which is perfect, but the events are not tracked to a certain 'event'; they are simply defined in congruent spatial reference with the wave event. Ideally, I would prefer to be able to set an event, much like in your gantt charts, and then have stuff referenced off of that.

an example might be as follows: this describes a clock, databus, and data ready signal. The databus and signal will reference the clock line for their timing. At some amount of clock cycles, the databus will fill with a value. Once filled it will be 'X' many clock cycles until the ready signal is sent.

clock "clk" as myClk

myClk period is 200ns 

Binary Bus "Data Bus" as db

Binary Signal "Data Ready" as dr



+4 myClk is 0x354 as dataStart


0 is low

+5 myClk from dataStart is high

Please let me know if something like this is doable, I would love to help in any way I can to see this stuff worked out. If there are already things in place for this, please let me know, and I would be happy to create examples for the website.

1 Answer

0 votes
answered Feb 26, 2019 by plantuml (295,000 points)
selected Jun 3, 2022 by awschult
Best answer

Thanks for the suggestions.

It's going to take some times to do all these, and it's not sure that we will get something as complete as WaveDrom.

We would like to keep the language logical and not too cryptic.

In last beta http://beta.plantuml.net/plantuml.jar we added the concept of "clock" and "binary" to that you can now have:

 clock clk with period 50
 binary "Signal3" as S3
 concise "Signal1" as S1
 robust "Signal2" as S2
 S1 is 0
 S2 is 0
 S1 is 1
 S3 is high
 S3 is down
 S1 is 1
 S2 is 1
 S3 is 1
 S3 is down


 clock clk with period 50
 concise "Signal1" as S1
 robust "Signal2" as S2
 binary "Signal3" as S3
 S1 is 0
 S2 is 0
 S3 is 1
 S1 is 1
 S3 is high
 S3 is down
 S1 is 1
 S2 is 1
 S3 is 1
 S3 is down

You can try those examples and make suggestions for enhancing the language itself. Somehow, this is the most difficult part : getting something consistent, flexible and easy to understand.

commented Feb 27, 2019 by kaushalmodi (260 points)
Can you please change the "down" keyword to "low"? It's more common to say that. Thanks!
commented Feb 27, 2019 by anonymous
That was the first thing that also came to my mind :)
commented Feb 27, 2019 by plantuml (295,000 points)
By chance it's currently working with current beta because everything different than "high" or "1" is interpreted as "0" :-)
commented Mar 1, 2019 by awschult (360 points)
I just grabbed the beta. This is a fantastic start! I like how the binary signals shrink their vertical spacing to fit better on screen. And your syntax is a lot more clear than what  I initially came up with. Being able to specify a specific clock cycle to fire on is a great attribute that puts this ahead of WaveDrom.

A few notes about the beta, which you might already know about, the binary signals do not have any kind of label; so I do not know which signal is which. The "concise" signal is perfect as a databus, however, the display of the signal name adds a lot of vertical space which disrupts the overall visual appeal of the compact binary signals. Below is a real example of what my coworkers see on a daily basis from our circuit simulations.


The signal names are displayed on the left, and every signal has the same vertical spacing. With that many databusses, the extra vertical white space would inflate the graph significantly.

Another thing that I noticed in that image is the use of pulses, or change in duty cycle. In the image, there is a "setpc" signal. This is a small duty cycle clock pulse. it would be a very nice feature to be able to specify a clock signal with a 50 ms period (as the beta has), but then give a parameter for the duty cycle.

Currently the duty cycle of the clock in the beta is 50% (half on half off), but in the real world, sometimes we want a duty cycle of 40% on 60% off. it would be amazing if we could also specify a duty cycle for the clock, so we can show pulses down to 10% even.
commented Mar 15, 2019 by plantuml (295,000 points)
We still are making slow progress.
With last beta http://beta.plantuml.net/plantuml.jar you can now have

clock clk with period 50 pulse 10

In the future, we will add an option to put signal name on the left to have a more "compact" graph.
commented Mar 30, 2020 by awschult (360 points)
Was there ever syntax added to put the signal name on the left for a more "compact" graph?
commented Oct 5, 2021 by The-Lu (67,080 points)

Hello @awschult,

For the "signal name" see:

clock "Clock" as clk with period 50


commented Mar 23, 2022 by EtienneA (180 points)
Ability to break a binary and a concise is still missing. There are cases like SPI transactions where you want to show the beginning and the end of the transaction, without needing to show all bits (too long diagram). Having the ability to insert some "hashing" in the signal (e.g. ‾‾‾‾__//__‾‾‾‾‾) would be great. If this comes with the constraint of not being able to display the timeline, that's fine for me as a start.